1. Field of the Invention
The present invention relates to a method of measuring a gate channel length of a metal-oxide semiconductor (MOS) transistor, and more specifically, to a method of obtaining the value of an unknown gate channel length of a MOS transistor by measuring an inverse gate leakage current of a sample MOS transistor with a known gate channel length and using a predetermined equation.
2. Description of the Prior Art
With the development of very large scale integration (VLSI), the low electricity consumption and high integration of metal-oxide-semiconductor (MOS) transistors allows them to be widely applied in the semiconductor process. Usually, a MOS transistor comprises a gate and two semiconductor regions, called a source and drain located on each side of a capacitor with an electrical characteristic opposite to that of the silicon substrate. The major structure of the gate is composed of a gate oxide layer and a gate conductive layer. When a proper bias is added to the gate, the MOS transistor can be regarded as a solid switch to control the connection of current.
In MOS transistor fabrication, a typical method to test a MOS transistor is frequently employed to continuously test the fabricated MOS transistors in every step so as to maintain the quality of every MOS transistor. Normally several test keys distributed in a periphery region of a die that is to be tested is provided, and a testing sample MOS transistor or a testing deposition layer is simultaneously fabricated in the test key area, typically formed on a scribe line between dies, with an actual MOS transistor so that the quality of the actual MOS transistor is judged by the performance of the testing sample MOS transistor. The quality, specification and functions of the actual MOS transistor therefore are well controlled, and the yield rate of MOS transistor manufacturing is consequently improved. As the semiconductor integration processes turn more and more complicated, it becomes one of the most important issues in the semiconductor industry to infer the characteristics of the MOS transistor correctly by measuring the value of an effective channel length of the MOS transistor precisely. Furthermore, the effective channel length of the MOS transistor is also one of the most important references for computer-aided designing (CAD).
According to the prior art, a scanning electron microscope (SEM) or a transmission electron microscopy (TEM) is frequently employed to measure the gate channel length of a MOS transistor. However, as semiconductor manufacturing technology progresses, process line width decreases to even less than 0.13 microns, so that errors often occur to the measuring results of the gate channel lengths of MOS transistors done by the SEM or TEM due to the scale limitations of the SEM and TEM. Consequently, the quality of the fabricated MOS transistors is seriously flawed, and the manufacturing yield rate is reduced as well. Therefore, it is indeed important to find out an alternative method to measure the gate channel length of a MOS transistor more precisely.